The 'GTL16612 devices are 18-bit UBT transceivers that provide LVTTL-to-GTL/GTL+
and GTL/GTL+-to-LVTTL signal-level translation. They combine D-type flip-flops and D-type latches
to allow for transparent, latched, clocked, and clock-enabled modes of data transfer identical to
the '16601 function. The devices provide an interface between cards operating at LVTTL logic
levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct
result of the reduced output swing (<1 V), reduced input threshold levels, and OEC circuitry.
The user has the flexibility of using these devices at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred
higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative
of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V
tolerant. VREF is the reference input voltage for the B port.
VCC (5 V) supplies the internal and GTL circuitry while VCC (3.3 V) supplies the LVTTL output buffers.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable(LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB\ and CEBA\)
inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is
low, the A data is latched if CEAB\ is low and CLKAB is held at a high or low logic level. If LEAB is low, the A data
is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB\ also is low. When OEAB\ is low, the
outputs are active. When OEAB\ is high, the outputs are in the high-impedance state. Data flow for B to A is
similar to that for A to B, but uses OEBA\, LEBA, CLKBA, and CEBA\.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
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