These devices are positive-edge-triggered D-type
flip-flops with a common enable input. The
HCT273 devices are similar to the HCT377
devices, but feature a common clear enable
(CLR)\ input instead of a latched clock.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
Q outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the positive-going pulse. When CLK is at either
the high or low level, the D input has no effect at
the output. The circuits are designed to prevent
false clocking by transitions at (CLR)\.
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