See datasheet for actual packaging/pinout drawings

Packaging

Package | PIN:

N | 16

Temp:

C (0 to 70)

ECO Plan:

Pb-Free (RoHS)

SN74LS112AN


Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset

TI Store Price:

 
 
Qty.Price
1 - 9 $ 0.71
10 - 24 $ 0.63
25 - 99 $ 0.57
100 - 249 $ 0.50
250 - 499 $ 0.45
500 - 749 $ 0.36
750 - 999 $ 0.29
1000 - 9999 $ 0.24

Adjust your quantity during checkout

Texas Instruments SN74LS112AN

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The SN54LS112A and SN54S112 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS112A and SN74S112A are characterized for operation from 0°C to 70°C.

  View datasheet
View product folder

Order SummaryEdit >
Subtotal: $0.00
Shipping & Handling: -
Total (USD): $0.00