These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378,
and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively,
but feature a common enable instead of a common clear.
Information at the D inputs meeting the setup time requirements is transferred
to the Q outputs on the positive-going edge of the clock pulse if the enable
input G\ is low. Clock triggering occurs at a particular voltage
level and is not directly related to the transition time of the positive-going
pulse. When the clock input is at either the high or low level, the D input
signal has no effect at the output. The circuits are designed to prevent false
clocking by transitions at the G\ input.
These flip-flops are guaranteed to respond to clock frequencies ranging
from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz.
Typical power dissipation is 10 milliwatts per flip-flop.
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