These devices each contain an 8-bit binary counter that feeds an 8-bit
storage register. The storage register has parallel outputs. Separate clocks
are provided for both the binary counter and storage register. The binary
counter features a direct clear input CCLR\ and a count enable input CCKEN\. For cascading, a ripple carry output RCO\ is provided.
Expansion is easily accomplished for two stages by connecting RCO\
of the first stage to CCKEN\ of the second stage. Cascading for
larger count chains can be accomplished by connecting RCO\ of each
stage to CCK of the following stage.
Both the counter and register clocks are positive-edge triggered. If the
user wishes to connect both clocks together, the counter state will always
be one count ahead of the register. Internal circuitry prevents clocking from
the clock enable.
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