These devices each contain an 8-bit serial-in, parallel-out shift register
that feeds an 8-bit D-type storage register. The storage register has parallel
3-state ('LS595) or open-collector ('LS596) outputs. Separate clocks are provided
for both the shift register and the storage register. The shift register has
a direct-overriding clear, serial input, and serial output pins for cascading.
Both the shift register and storage register clocks are positive-edge triggered.
If the user wishes to connect both clocks together, the shift register state
will always be one clock pulse ahead of the storage register.
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