See datasheet for actual packaging/pinout drawings


Package | PIN:

PW | 16


Q (-40 to 125)

ECO Plan:

Green (RoHS & no Sb/Br)


Parallel-Load 8-Bit Shift Registers

TI Store Price:

1 - 9 $ 0.43
10 - 24 $ 0.36
25 - 99 $ 0.35
100 - 249 $ 0.23
250 - 499 $ 0.23
500 - 749 $ 0.21
750 - 999 $ 0.16
1000 - 9999 $ 0.12

Adjust your quantity during checkout

Texas Instruments SN74LV165APWR

The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.

When the devices are clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. The ’LV165A devices feature a clock-inhibit function and a complemented serial output, QH.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and clock inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH accomplishes clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. The parallel inputs to the register are enabled while SH/LD is held low, independently of the levels of CLK, CLK INH, or SER.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

View datasheet
View product folder
Order SummaryEdit >
Subtotal: $0.00
Shipping & Handling: -
Total (USD): $0.00