See datasheet for actual packaging/pinout drawings

Packaging

Package | PIN:

PW | 16

Temp:

Q (-40 to 125)

ECO Plan:

Green (RoHS & no Sb/Br)

SN74LVC112APWR


Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset

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Qty.Price
1 - 9 $ 0.84
10 - 24 $ 0.73
25 - 99 $ 0.66
100 - 249 $ 0.58
250 - 499 $ 0.51
500 - 749 $ 0.38
750 - 999 $ 0.29
1000 - 9999 $ 0.21

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Texas Instruments SN74LVC112APWR

This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation.

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