The SN74LVT8996 10-bit addressable scan port (ASP) is a member of the Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most SCOPE devices, the ASP is not a boundary-scannable device, rather, it applies TIs addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level.
This device is functionally equivalent to the ABT8996 ASPs. Additionally, it is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to interface to 5-V masters and/or targets.
Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP signals
to a set of secondary TAP signals - for example, to interface backplane TAP signals to a board-level TAP. The ASP
provides all signal buffering that might be required at these two interfaces. When primary and secondary TAPs are
connected, only a moderate propagation delay is introduced - no storage/retiming elements are inserted. This
minimizes the need for reformatting board-level test vectors for in-system use.
Most operations of the ASP are synchronous to the primary test clock (PTCK) input. PTCK is always buffered directly
onto the secondary test clock (STCK) output.
Upon power up of the device, the ASP assumes a condition in which the primary TAP is disconnected from the
secondary TAP (unless the bypass signal is used, as below). This reset condition also can be entered by the
assertion of the primary test reset (PTRST)\ input or by use of shadow protocol. PTRST\ is always buffered directly
onto the secondary test reset (STRST)\ output, ensuring that the ASP and its associated secondary TAP can be reset
When connected, the primary test data input (PTDI) and primary test mode select (PTMS) input are buffered onto
the secondary test data output (STDO) and secondary test mode select (STMS) output, respectively, while the
secondary test data input (STDI) is buffered onto the primary test data output (PTDO). When disconnected, STDO
is at high impedance, while PTDO is at high impedance, except during acknowledgment of a shadow protocol. Upon
disconnect of the secondary TAP, STMS holds its last low or high level, allowing the secondary TAP to be held in
its last stable state. Upon reset of the ASP, STMS is high, allowing the secondary TAP to be synchronously reset
to the Test-Logic-Reset state.
In system, primary-to-secondary connection is based on shadow protocols that are received and acknowledged on
PTDI and PTDO, respectively. These protocols can occur in any of the stable TAP states other than Shift-DR or
Shift-IR (i.e., Test-Logic-Reset, Run-Test/Idle, Pause-DR or Pause-IR). The essential nature of the protocols is to
receive/transmit an address via a serial bit-pair signaling scheme. When an address is received serially at PTDI that
matches that at the parallel address inputs (A9-A0), the ASP serially retransmits its address at PTDO as an
acknowledgment and then assumes the connected (ON) status, as above. If the received address does not match
that at the address inputs, the ASP immediately assumes the disconnected (OFF) status without acknowledgment.
The ASP also supports three dedicated addresses that can be received globally (that is, to which all ASPs respond)
during shadow protocols. Receipt of the dedicated disconnect address (DSA) causes the ASP to disconnect in the
same fashion as a nonmatching address. Reservation of this address for global use ensures that at least one
address is available to disconnect all receiving ASPs. The DSA is especially useful when the secondary TAPs of
multiple ASPs are to be left in different stable states. Receipt of the reset address (RSA) causes the ASP to assume
the reset condition, as above. Receipt of the test-synchronization address (TSA) causes the ASP to assume a
connect status (MULTICAST) in which PTDO is at high impedance but the connections from PTMS to STMS and
PTDI to STDO are maintained to allow simultaneous operation of the secondary TAPs of multiple ASPs. This is
useful for multicast TAP-state movement, simultaneous test operation (such as in Run-Test/Idle state), and
scanning of common test data into multiple like scan chains. The TSA is valid only when received in the Pause-DR
or Pause-IR TAP states.
Alternatively, primary-to-secondary connection can be selected by assertion of a low level at the bypass (BYP)\ input.
This operation is asynchronous to PTCK and is independent of PTRST\ and/or power-up reset. This bypassing
feature is especially useful in the board-test environment, since it allows the board-level automated test equipment
(ATE) to treat the ASP as a simple transceiver. When the BYP\ input is high, the ASP is free to respond to shadow
protocols. Otherwise, when BYP is low, shadow protocols are ignored.
Whether the connected status is achieved by use of shadow protocol or by use of BYP\, this status is indicated by
a low level at the connect (CON)\ output. Likewise, when the secondary TAP is disconnected from the primary TAP,
the CON\ output is high.
View datasheet View product folder