The 'LVTH18504A and 'LVTH182504A scan test devices with 20-bit
universal bus transceivers are members of the Texas Instruments (TI)
SCOPE testability integrated-circuit family. This family of devices
supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of
complex circuit-board assemblies. Scan access to the test circuitry
is accomplished via the 4-wire test access port (TAP) interface.
Additionally, these devices are designed specifically for
low-voltage (3.3-V) VCC operation, but with the capability
to provide a TTL interface to a 5-V system environment.
In the normal mode, these devices are 20-bit universal bus
transceivers that combine D-type latches and D-type flip-flops to
allow data flow in transparent, latched, or clocked modes. The test
circuitry can be activated by the TAP to take snapshot samples of the
data appearing at the device pins or to perform a self-test on the
boundary-test cells. Activating the TAP in the normal mode does not
affect the functional operation of the SCOPE universal bus
Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA),
clock-enable ( and ), and clock (CLKAB and CLKBA)
inputs. For A-to-B data flow, the device operates in the transparent
mode when LEAB is high. When LEAB is low, the A-bus data is latched
while is high and/or
CLKAB is held at a static low or high logic level. Otherwise, if LEAB
is low and is low, A-bus
data is stored on a low-to-high transition of CLKAB. When is low, the B outputs are active.
When is high, the B
outputs are in the high-impedance state. B-to-A data flow is similar
to A-to-B data flow, but uses the , LEBA,, and
In the test mode, the normal operation of the SCOPE universal bus
transceivers is inhibited, and the test circuitry is enabled to
observe and control the I/O boundary of the device. When enabled, the
test circuitry performs boundary-scan test operations according to
the protocol described in IEEE Std 1149.1-1990.
Four dedicated test pins are used to observe and control the
operation of the test circuitry: test data input (TDI), test data
output (TDO), test mode select (TMS), and test clock (TCK).
Additionally, the test circuitry performs other testing functions,
such as parallel-signature analysis (PSA) on data inputs and
pseudo-random pattern generation (PRPG) from data outputs. All
testing and scan operations are synchronized to the TAP interface.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
The B-port outputs of 'LVTH182504A, which are designed to source
or sink up to 12 mA, include equivalent 25- series resistors to reduce
overshoot and undershoot.
The SN54LVTH18504A and SN54LVTH182504A are characterized for
operation over the full military temperature range of -55°C to
125°C. The SN74LVTH18504A and SN74LVTH182504A are characterized
for operation from -40°C to 85°C.
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