See datasheet for actual packaging/pinout drawings

Packaging

Package | PIN:

DGG | 48

Temp:

C (0 to 70)

ECO Plan:

Green (RoHS & no Sb/Br)

SN75LVDS86DGG


FlatLink(TM) Receiver

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Texas Instruments SN75LVDS86DGG

The SN75LVDS86 FlatLink receiver contains three serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, '83, '84, or '85, over four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage TTL (LVTTL) synchronous data at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN75LVDS86 presents valid data on the falling edge of the output clock (CLKOUT).

The SN75LVDS86 requires only four line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level.

The LVDS receivers of the SN75LVDS86 include an open-circuit fail-safe design such that when the inputs are not connected to an LVDS driver, the receiver outputs go to a low-level. This occurs even when the line is differentially terminated at the receiver inputs.

The SN75LVDS86 is characterized for operation over ambient free-air temperatures of 0°C to 70°C.

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