The SP16160CH1RB demonstrates a high-IF sampling receiver subsystem that provides signal amplification, digitization and clocking as used in wireless infrastructure systems. The subsystem includes the ADC16DV160 analog-to-digital converter (ADC), LMH6517 Digitally-controlled Variable-Gain Amplifier (DVGA) and LMK04031B precision clock conditioner.
In the signal path, the subsystem provides impedance-matched, single-to-differential conversion through a 1:4 transformer and a 31.5 dB amplification gain range in 0.5 dB steps through the DVGA. The anti-aliasing filter at the output of the DVGA provides noise filtering and over 40 dB harmonic suppression by selecting the 20 MHz signal band centered at 192 MHz. The signal is then sampled and quantized by the ADC into 16-bit words using a 153.6 MHz CMOS clock.
In the clock path, a LMK04031B clock conditioning circuit operates with a 61.44 MHz reference oscillator and 76.8 MHz VCXO to provide the 153.6 MHz CMOS sampling clock. The clock output is also filtered and buffered to provide very low broadband noise for less than 200 fs total jitter over the clock input bandwidth of the ADC.