See datasheet for actual packaging/pinout drawings

Packaging

Package | PIN:

PM | 64

Temp:

C (0 to 70)

ECO Plan:

Green (RoHS & no Sb/Br)

TL16C750PM


Single UART with 64-Byte Fifos, Auto Flow Control, Low-Power Modes

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Texas Instruments TL16C750PM

The TL16C750 is a functional upgrade of the TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the TL16C750, like the TL16C550C, can be placed in an alternate mode (FIFO mode). This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 64 bytes including three additional bits of error status per byte for the receiver FIFO. The user can choose between a 16-byte FIFO mode or an extended 64-byte FIFO mode. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow through the RTS\ output and the CTS\ input signals (see Figure 1).

The TL16C750 performs serial-to-parallel conversion on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE status at any time. The ACE includes complete modem control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.

The TL16C750 ACE includes a programmable baud rate generator capable of dividing a reference clock by divisors from 1 to (216 - 1) and producing a 16× reference clock for the internal transmitter logic. Provisions are also included to use this 16× clock for the receiver logic. The ACE accommodates a 1-Mbaud serial rate (16-MHz input clock) so a bit time is 1 us and a typical character time is 10 us (start bit, 8 data bits, stop bit).

Two of the TL16C450 terminal functions have been changed to TXRDY\ and RXRDY\, which provide signaling to a direct memory access (DMA) controller.

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