See datasheet for actual packaging/pinout drawings

Packaging

Package | PIN:

RGE | 24

Temp:

S (-40 to 100)

ECO Plan:

Green (RoHS & no Sb/Br)

TLK1102ERGET


11.3-Gbps Dual Channel Cable and PC Board Equalizer

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Texas Instruments TLK1102ERGET

The TLK1102E is a versatile and flexible high-speed dual-channel equalizer for applications in digital high-speed links with data rates up to 11.3Gbps.

The TLK1102E can be configured in many ways through its two-wire serial interface, available through the SDA and the SCL pins, to optimize its performance. The configurable parameters include the output de-emphasis settable from 0 to 7dB, the output differential voltage swing settable from 225 to 1200mVp-p, the input equalization level settable for 0 to 20 meters of 24-AWG twinaxial cable, 0 to 40 inches of FR-4 PCB interconnect, or equivalent interconnect, the input filter bandwidth settable from 4.5 to 11GHz, and the LOS (loss of signal) assert voltage level.

Alternatively, the TLK1102E can be configured using its configuration pins in two modes selectable using the MODE pin. In Pin Control Mode 1, a common setting can be set for the two channels for the output de-emphasis level and the interconnect length using the DE pin and LN0, LN1 pins respectively. In Pin Control Mode 2, those parameters can be set individually for the two channels using DEA, DEB, LNA, and LNB pins. In both modes only a common setting is available for the output voltage swing using the SWG pin. For Pin Control Mode 2 the typical LOS assert and de-assert voltage levels are fixed at 90mVp-p and 150mVp-p respectively with 4.0dB hysteresis.

The outputs can be disabled using the DISA and DISB pins. The DISA/DISB pins and the LOSA/LOSB pins can be connected together to implement an external output squelch function. The TLK1102E implements an internal output squelch function that can be enabled using the two-wire serial interface. In addition, a special fast auto-squelch function can be selected through the two-wire serial interface when needed to support SAS and SATA out-of-band (OOB) signals.

The POLA and POLB pins can be used to reverse the polarity of the OUTA+/OUTA- and OUTB+/OUTB- pins respectively.

The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal swings as high as 1600mVp-p differential. The low-frequency cut-off is low enough to support low-frequency control signals such as SAS and SATA OOB signals. The loss-of-signal detection and output disable functions are carefully designed to meet SAS/SATA OOB signal timing constraints.

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