See datasheet for actual packaging/pinout drawings

Packaging

Package | PIN:

RGE | 24

Temp:

I (-40 to 85)

ECO Plan:

Green (RoHS & no Sb/Br)

TLV320ADC3100IRGER


Low-Power Stereo Analog-to-Digital Converter (ADC) for Voice-Activated Systems and Portable Audio

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1 - 9 $ 2.65
10 - 24 $ 2.39
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100 - 249 $ 1.95
250 - 499 $ 1.83
500 - 749 $ 1.55
750 - 999 $ 1.31
1000 - 9999 $ 1.25

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Texas Instruments TLV320ADC3100IRGER

The TLV320ADC3100 is a low-power, stereo audio analog-to-digital converter (ADC) supporting sampling rates from 8 kHz to 96 kHz with an integrated programmable-gain amplifier (PGA) providing up to 40-dB analog gain or automatic gain control (AGC). Front-end input coarse attenuation of 0 dB, –6 dB, or off, is also provided. The inputs are programmable in a combination of single-ended or fully differential configurations. Extensive register-based power control is available via an I2C interface, enabling mono or stereo recording. The TLV320ADC3100 integrates programable channel gain, digital volume control, a phase-locked loop (PLL), programmable biquad filters, and low latency filter modes. Pre-programmed built-in processing blocks (PRBs) that can be chosen based on the specific application needs, allows optimization of performance and power. Low power consumption coupled with its flexibility make the TLV320ADC3100 ideal for battery-powered portable equipment. The TLV320ADC3100 is form-factor and software compatible with the TLV320ADC3101.

The AGC programs to a wide range of attack (7 ms to 1.4 s) and decay (50 ms to 22.4 s) times. A programmable noise-gate function is included to avoid noise pumping. Low-latency interrupt identification register (IIR) filters optimized for voice and telephony are available, as well as linear-phase finite impulse response (FIR) filters optimized for audio. Programmable IIR filters are also available and can be used for sound equalization, or to remove noise components. The audio serial bus can be programmed to support I2S, left-justified, right-justified, digital signal processor (DSP), pulse code modulation (PCM), and time-division multiplexing (TDM) modes. The audio bus can be operated in either master or slave mode.

A programmable integrated PLL is included for flexible clock generation and provides support for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, including the most popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz system clocks.

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