The TLV320AIC3253 (sometimes referred to as the AIC3253) is a flexible, low-power, low-voltage stereo audio codec with digital microphone inputs and programmable outputs, PowerTune capabilities,
fully-programmable miniDSP, fixed predefined and parameterizable signal processing blocks, integrated
PLL, integrated LDO and flexible digital interfaces. Extensive register-based control of power, input/output channel configuration, gains, effects, pin-multiplexing and clocks is included, allowing the
device to be precisely targeted to its application.
Combined with the advanced PowerTune technology, the device can cover operations from 8kHz mono voice playback to stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and telephony applications.
The record path of the TLV320AIC3253 consists of a stereo digital microphone PDM interface (not available when using SPI control interface) typically used at 64Fs or 128Fs.
The playback path offers signal processing blocks for filtering and effects, true differential output signal, flexible mixing of DAC and analog input signals as well as programmable volume controls. The TLV320AIC3253 contains two high-power output drivers which can be configured in multiple ways, including stereo, and mono BTL. The integrated PowerTune technology allows the device to be tuned to just the right power-performance trade-off. Mobile applications frequently have multiple use cases requiring very low-power operation while being used in a mobile environment. When used in a docked environment power consumption typically is less of a concern while lowest possible noise is important. With PowerTune the TLV320AIC3253 can address both cases.
The voltage supply range for the TLV320AIC3253 for analog is 1.5V–1.95V, and for digital it is 1.26V–1.95V. To ease system-level design, a low-dropout regulator (LDO) is integrated to generate the appropriate analog supply from input voltages ranging from 1.8V to . Digital I/O voltages are supported in the range of 1.1V–3.6V.
The required internal clock of the TLV320AIC3253 can be derived from multiple sources, including the MCLK pin, the BCLK pin, the GPIO pin or the output of the internal PLL, where the input to the PLL again can be derived from the MCLK pin, the BCLK or GPIO pins. Although using the internal, fractional PLL ensures the availability of a suitable clock signal, it is not recommended for the lowest power settings. The PLL is highly programmable and can accept available input clocks in the range of 512kHz to 50MHz.
The device is available in the 2.7mm × 2.7mm WCSP or the 4mm × 4mm QFN package.
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