The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP)
product family and is designed for low-power applications.
The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The
C55x™ DSP architecture achieves high performance and low power through increased parallelism and
total focus on power savings. The CPU supports an internal bus structure that is composed of one
program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses,
and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to
perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also
includes four DMA controllers, each with 4 channels, providing data movement for 16-independent
channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer
per cycle, in parallel and independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x
17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit
(ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control,
providing the ability to optimize parallel activity and power consumption. These resources are
managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.
The C55x CPU supports a variable byte width instruction set for improved code density.
The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and
queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs
tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected
pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional
The general-purpose input and output functions along
with the 10-bit SAR ADC provide sufficient pins for status, interrupts, and bit I/O for LCD
displays, keyboards, and media interfaces. Serial media is supported through two MultiMedia
Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port
Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a
Universal Asynchronous Receiver/Transmitter (UART) interface.
The device peripheral set includes an external memory interface (EMIF) that provides
glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed,
high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional
peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time
clock (RTC). This device also includes three general-purpose timers with one configurable as a
watchdog timer, and an analog phase-locked loop (APLL) clock generator.
In addition, the device includes a tightly-coupled FFT Hardware
Accelerator. The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power of 2)
real and complex-valued FFTs.
The device includes one integrated LDO (ANA_LDO) to provide regulated
1.3 V to the DSP PLL (VDDA_PLL) and 10-bit SAR
ADC(VDDA_ANA). Note: ANA_LDO can only
provide a regulated 1.3 V. When the DSP PLL requires 1.4 V (PLLOUT > 120 MHz), an external
supply is required to supply 1.4 V to the DSP PLL (VDDA_PLL).
The device is supported by the industry’s award-winning eXpressDSP™, Code Composer
Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard,
and the industry’s largest third-party network. Code Composer Studio IDE features code generation
tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers,
and evaluation modules. The device is also supported by the C55x DSP Library which features more
than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support
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