The TMS320DM6467 (also referenced as DM6467) leverages TI's DaVinci™
technology to meet the networked media encode and decode digital media processing
needs of next-generation embedded devices.
The DM6467 enables OEMs and ODMs to quickly bring to market devices featuring
robust operating systems support, rich user interfaces, high processing
performance, and long battery life through the maximum flexibility of a fully
integrated mixed processor solution.
The dual-core architecture of the DM6467 provides benefits of both DSP and
Reduced Instruction Set Computer (RISC) technologies, incorporating a
high-performance TMS320C64x+ DSP core and an ARM926EJ-S core.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit
instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses
pipelining so that all parts of the processor and memory system can operate
The ARM core incorporates:
- A coprocessor 15 (CP15) and protection module
- Data and program Memory Management Units (MMUs) with table look-aside
- Separate 16K-byte instruction and 8K-byte data caches. Both are four-way
associative with virtual index virtual tag (VIVT).
The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation
in the TMS320C6000™ DSP platform. It is based on an enhanced version of the
second-generation high-performance, advanced very-long-instruction-word (VLIW)
architecture developed by Texas Instruments (TI), making these DSP cores an
excellent choice for digital media applications. The C64x is a code-compatible
member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the
C64x+ DSP with added functionality and an expanded instruction set.
Any reference to the C64x DSP or C64x CPU also applies, unless otherwise
noted, to the C64x+ DSP and C64x+ CPU, respectively.
With performance of up to 5832 million instructions per second (MIPS) at a
clock rate of 729 MHz, the C64x+ core offers solutions to high-performance DSP
programming challenges. The DSP core possesses the operational flexibility of
high-speed controllers and the numerical capability of array processors. The
C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length
and eight highly independent functional units-two multipliers for a 32-bit
result and six arithmetic logic units (ALUs). The eight functional units include
instructions to accelerate the performance in video and imaging applications.
The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a
total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for
a total of 4752 MMACS. For more details on the C64x+ DSP, see the
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide(literature
The DM6467 also has application-specific hardware logic, on-chip memory, and
additional on-chip peripherals similar to the other C6000 DSP platform devices.
The DM6467 core uses a two-level cache-based architecture. The Level 1 program
cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D)
is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2)
consists of an 512K-bit memory space that is shared between program and data
space. L2 memory can be configured as mapped memory, cache, or combinations of
The peripheral set includes: a configurable video port; a 10/100/1000 Mb/s
Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; a 4-bit
transfer/4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus
interface; a multichannel audio serial port (McASP0) with 4 serializers; a
secondary multichannel audio serial port (McASP1) with a single transmit
serializer; 2 64-bit general-purpose timers each configurable as 2 independent
32-bit timers; 1 64-bit watchdog timer; a configurable 32-bit host port
interface (HPI); up to 33-pins of general-purpose input/output (GPIO) with
programmable interrupt/event generation modes, multiplexed with other
peripherals; 3 UART/IrDA/CIR interfaces with modem interface signals on UART0; 2
pulse width modulator (PWM) peripherals; an ATA/ATAPI-6 interface; a 33-MHz
peripheral component interface (PCI); and 2 external memory interfaces: an
asynchronous external memory interface (EMIFA) for slower memories/peripherals,
and a higher speed synchronous memory interface for DDR2.
The Ethernet Media Access Controller (EMAC) provides an efficient interface
between the DM6467 and the network. The DM6467 EMAC support both 10Base-T and
100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or
full-duplex mode; and 1000Base-TX (1 Gbps) in full-duplex mode with hardware
flow control and quality of service (QOS) support.
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO
addresses in order to enumerate all PHY devices in the system. Once a PHY
candidate has been selected by the ARM, the MDIO module transparently monitors
its link state by reading the PHY status register. Link change events are stored
in the MDIO module and can optionally interrupt the ARM, allowing the ARM to
poll the link status of the device without continuously performing costly MDIO
The PCI, HPI, I2C, SPI, USB2.0, and VLYNQ ports allow the DM6467 to easily
control peripheral devices and/or communicate with host processors.
The DM6467 also includes a High-Definition Video/Imaging Co-processor
(HDVICP) and Video Data Conversion Engine (VDCE) to offload many video and
imaging processing tasks from the DSP core, making more DSP MIPS available for
common video and imaging algorithms. For more information on the HDVICP enhanced
codecs, such as H.264 and MPEG4, please contact your nearest TI sales
The rich peripheral set provides the ability to control external peripheral
devices and communicate with external processors. For details on each of the
peripherals, see the related sections later in this document and the associated
peripheral reference guides.
The DM6467 has a complete set of development tools for both the ARM and DSP.
These include C compilers, a DSP assembly optimizer to simplify programming and
scheduling, and a Windows™ debugger interface for visibility into source code
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