The TMS320VC5409A fixed-point, digital signal processor (DSP) (hereafter
referred to as the 5409A unless otherwise specified) is based on an advanced
modified Harvard architecture that has one program memory bus and three data
memory buses. This processor provides an arithmetic logic unit (ALU) with a high
degree of parallelism, application-specific hardware logic, on-chip memory, and
additional on-chip peripherals. The basis of the operational flexibility and
speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program
instructions and data, providing a high degree of parallelism. Two read
operations and one write operation can be performed in a single cycle.
Instructions with parallel store and application-specific instructions can fully
utilize this architecture. In addition, data can be transferred between data and
program spaces. Such parallelism supports a powerful set of arithmetic, logic,
and bit-manipulation operations that can all be performed in a single machine
cycle. The 5409A also includes the control mechanisms to manage interrupts,
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