See datasheet for actual packaging/pinout drawings

Packaging

Package | PIN:

DB | 24

Temp:

Q (-40 to 125)

ECO Plan:

Green (RoHS & no Sb/Br)

TPIC44L02DB


4-Channel Serial/Parallel Low-Side Pre-FET Driver

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Texas Instruments TPIC44L02DB

The TPIC44L01, TPIC44L02, and TPIC44L03 are low-side predrivers that provide serial and parallel input interfaces to control four external FET power switches such as offered in the TI TPIC family of power arrays. These devices are designed primarily for low-frequency switching, inductive load applications such as solenoids and relays. Fault status for each channel is available in a serial-data format. Each driver channel has independent off-state open-load detection and on-state shorted-load/short-to-battery detection. Battery overvoltage and undervoltage detection and shutdown is provided on the TPIC44L01/L02. On the TPIC44L03 driver, only over-battery voltage shutdown is provided. Each channel also provides inductive-voltage-transient protection for the external FET.

These devices provide control of output channels through a serial input interface or a parallel input interface. A command to enable the output from either interface enables the respective channels gate output to the external FET. The serial interface is recommended when the number of signals between the control device and the predriver must be minimized and the speed of operation is not critical. In applications where the predriver must respond very quickly or asynchronously, the parallel input interface is recommended.

For serial operation, the control device must transition CS\ from high to low to activate the serial input interface. When this occurs, SDO is enabled, fault data is latched into the serial interface, and the fault flag is refreshed.

Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must consist of at least four bits of data. In applications where multiple devices are cascaded together, the string of data must consist of four bits for each device. A high data bit turns the respective output channel on and a low data bit turns it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data consists of fault flags for shorted-load and open-load flags (bits 0\x963) for each of the four output channels. A high bit in the fault data indicates a fault and a low bit indicates that no fault is present for that channel. Fault register bits are set or cleared asynchronously to reflect the current state of the hardware. A fault must be present when CS\ is transitioned from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial register when CS\ is low. CS\ must be transitioned high after all of the serial data has been clocked into the device. A low-to-high transition of CS\ transfers the last four bits of serial data to the output buffer puts SDO in a high-impedance state and clears and reenables the fault register. The TPIC44L01/L02/L03 was designed to allow the serial input interfaces of multiple devices to be cascaded together to simplify the serial interface to the controller. Serial input data flows through the device and is transferred out SDO following the fault data in cascaded configurations.

For parallel operation, data is transferred directly from the parallel input interface IN0-IN3 to the respective GATE(0\x963) output asynchronously. SCLK or CS\ is not required for parallel control. A 1 on the parallel input turns the respective channel on, where a 0 turns it off. Note that either the serial input interface or the parallel input interface can enable a channel. Under parallel operation, fault data must still be collected through the serial data interface.

The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions in the the on and off states respectively. These devices offer the option of using an internally generated fault-reference voltage or an externally supplied fault-reference voltage through VCOMP for fault detection. The internal fault reference is selected by connecting VCOMPEN to GND and the external reference is selected by connecting VCOMPEN to VCC. The drain voltage is compared to the fault reference when the channel is turned on to detect shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted fault occurs using the TPIC44L01 or the TPIC44L03, the channel is turned off and a fault flag is sent to the control device as well as to the serial fault register bits. If a fault occurs while using the TPIC44L02, the channel transitions into a low-duty cycle, pulse-width-modulated (PWM) signal as long as the fault is present. Shorted-load fault conditions must be present for at least the shorted-load deglitch time, t(STBDG), to be flagged as a fault. A fault flag is sent to the control device as well as the serial fault register bits. More detail on fault detection operation is presented in the device operation section of this data sheet.

These devices provide protection from over-battery voltage and under-battery voltage conditions irrespective of the state of the output channels. When the battery voltage is greater than the overvoltage threshold or less than the undervoltage threshold, all channels are disabled and a fault flag is generated. Battery-voltage faults are not reported in the serial fault data. The outputs return to normal operation once the battery-voltage fault has been corrected. When an over-battery/under-battery voltage condition occurs, the device reports the battery fault, but disables fault reporting for open- and shorted-load conditions. Fault reporting for open- and shorted-load conditions are reenabled after the battery fault condition has been corrected.

These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect the FET. The clamp voltage is defined by the sum of VCC and turnon voltage of the external FET. The predriver also provides a gate-to-source voltage (VGS) clamp to protect the gate-source terminals of the power FET from exceeding their rated voltages. An external active low RESET\ is provided to clear all registers and flags in the device. GATE(0\x963) outputs are disabled after RESET\ has been pulled low.

These devices provide pulldown resistors on all inputs except CS\ and RESET\. A pullup resistor is used on CS\ and RESET\. View datasheet
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