See datasheet for actual packaging/pinout drawings

Packaging

Package | PIN:

D | 14

Temp:

I (-40 to 85)

ECO Plan:

Green (RoHS & no Sb/Br)

TPS2331ID


3-13V Single Hot-Swap IC w/ Power Good Report, Act-High Enable

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Texas Instruments TPS2331ID

The TPS2330 and TPS2331 are single-channel hot-swap controllers that use external N-channel MOSFETs as high-side switches in power applications. Features of these devices, such as overcurrent protection (OCP), inrush-current control, output-power status reporting, and the ability to discriminate between load transients and faults, are critical requirements for hot-swap applications.

The TPS2330/31 devices incorporate undervoltage lockout (UVLO) and power-good (PG) reporting to ensure the device is off at start-up and confirm the status of the output voltage rails during operation. An internal charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance the N-channel MOSFETs. The charge pump controls both the rise times and fall times (dV/dt) of the MOSFETs, reducing power transients during power up/down. The circuit-breaker functionality combines the ability to sense overcurrent conditions with a timer function; this allows designs such as DSPs, that may have high peak currents during power-state transitions, to disregard transients for a programmable period.

DISCH – DISCH should be connected to the source of the external N-channel MOSFET transistor connected to GATE. This pin discharges the load when the MOSFET transistor is disabled. They also serve as reference-voltage connection for internal gate-voltage-clamp circuitry.

ENABLE or ENABLE –  ENABLE for TPS2330 is active-low. ENABLE for TPS2331 is active-high. When the controller is enabled, GATE voltage powers up to turn on the external MOSFETs. When the ENABLE pin is pulled high for TPS2330 or the ENABLE pin is pulled low for TPS2331 for more than 50 µs, the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) when enabled and shuts down PREREG when disabled so that total supply current is much less than 5 µA.

FAULT  –  FAULT is an open-drain overcurrent flag output. When an overcurrent condition is sustained long enough to charge TIMER to 0.5 V, the device latches off and pulls FAULT low. In order to turn the device back on, either the enable pin must be toggled or the input power must be cycled.

GATE – GATE connects to the gate of the external N-channel MOSFET transistor. When the device is enabled, internal charge-pump circuitry pulls this pin up by sourcing approximately 15 µA. The turnon slew rates depend on the capacitance present at the GATE terminal. If desired, the turnon slew rates can be further reduced by connecting capacitors between this pin and ground. These capacitors also reduce inrush current and protect the device from false overcurrent triggering during power up. The charge-pump circuitry generates gate-to-source voltages of 9 V–12 V across the external MOSFET transistor.

IN – IN should be connected to the power source driving the external N-channel MOSFET transistor connected to GATE. The TPS2330/31 draws its operating current from IN, and remains disabled until the IN power supply has been established. The device has been constructed to support 3-V, 5-V, or 12-V operation.

ISENSE, ISET – ISENSE in combination with ISET implements overcurrent sensing for GATE. ISET sets the magnitude of the current that generates an overcurrent fault, through an external resistor connected to ISET. An internal current source draws 50 µA from ISET. With a sense resistor from IN to ISENSE, which is also connected to the drain of the external MOSFET, the voltage on the sense resistor reflects the load current. An overcurrent condition is assumed to exist if ISENSE is pulled below ISET. To ensure proper circuit breaker operation, VI(ISENSE) and VI(ISET) should never exceed VI(IN).

PWRGD – PWRGD signals the presence of undervoltage conditions on VSENSE. The pin is an open-drain output and is pulled low during an undervoltage condition. To minimize erroneous PWRGD responses from transients on the voltage rail, the voltage sense circuit incorporates a 20-µs deglitch filter. When VSENSE is lower than the reference voltage (about 1.23 V), PWRGD is active-low to indicate an undervoltage condition on the power-rail voltage. PWRGD may not correctly report power conditions when the device is disabled because there is no gate drive power for the PWRGD output transistor in the disable mode, or, in other words, PWRGD is floating. Therefore, PWRGD is pulled up to its pullup power supply rail in disable mode.

TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly recommended from TIMER to ground, to prevent any false triggering.

VREG – VREG is the output of an internal low-dropout voltage regulator, where IN1 is the input. The regulator is used to generate a regulated voltage source, less than 5.5 V, for the device. A 0.1-µF ceramic capacitor should be connected between VREG and ground to aid in noise rejection. In this configuration, on disabling the device, the internal low-dropout regulator also is disabled, which removes power from the internal circuitry and allows the device to be placed in low-quiescent-current mode. In applications where IN1 is less than 5.5 V, VREG and IN1 may be connected together. However, under these conditions, disabling the device may not place the device in low-quiescent-current mode, because the internal low-dropout voltage regulator is being bypassed, thereby keeping internal circuitry operational. If VREG and IN1 are connected together, a 0.1-µF ceramic capacitor between VREG and ground is not needed if IN1 already has a bypass capacitor of 1 µF to 10 µF.

VSENSE – VSENSE can be used to detect undervoltage conditions on external circuitry. If VSENSE senses a voltage below approximately 1.23 V, PWRGD is pulled low.

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