The TPS312x family of ultralow voltage processor supervisory circuits provides circuit initialization and timing supervision, primarily for DSP and processor-based systems.
During power-on, RESET is asserted when the supply voltage (VDD) becomes higher than 0.75 V. Thereafter, the supply voltage supervisor monitors VDD and keeps RESET output active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td = 180 ms, starts after VDD has risen above the threshold voltage (VIT).
When the supply voltage drops below the threshold voltage (VIT), the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage (VIT) set by a high precision internal voltage divider.
The TPS3123/5/6/8 devices incorporate a manual reset input, MR. A low level at MR causes RESET to become active. The TPS3124 devices do not have the input MR, but include a high-level output RESET same as the TPS3125 and TPS3126 devices. In addition, the TPS3123/4/8 have a watchdog timer that needs to be triggered periodically by a positive or negative transition at WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval ttout= 0.8 s, RESET output becomes active for the time period (td). This event also reinitializes the watchdog timer.
The circuits are available in a 5-pin SOT23-5 package. The TPS312x devices are characterized for operation over a temperature range of –40°C to +85°C.
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