The TPS3836, TPS3837, TPS3838 families of supervisory circuits provide circuit initialization and timing supervision, primarily for DSP and processor-based systems.
During power on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the supervisory circuit monitors VDD and keeps RESET output active as long as VDD remains below the threshold voltage VIT . An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time starts after VDD has risen above the threshold voltage VIT.
When CT is connected to GND a fixed delay time of typical 10 ms is asserted. When connected to VDD the delay time is typically 200 ms.
When the supply voltage drops below the threshold voltage VIT, the output becomes active (low) again.
All the devices of this family have a fixed-sense threshold voltage VIT set by an internal voltage divider.
The TPS3836 has an active-low push-pull RESET output. The TPS3837 has active-high push-pull RESET, and TPS3838 integrates an active-low open-drain RESET output.
The product spectrum is designed for supply voltages of 1.8 V, 2.5 V, 3 V, and 3.3 V. The circuits are available in a 5-pin SOT-23 package. The TPS3836-Q-Q1, TPS3837-Q-Q1, TPS3838-Q-Q1 families are characterized for operation over a temperature range of 40°C to 125°C.
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