See datasheet for actual packaging/pinout drawings

Package | PIN:

RSL | 48

Temp:

T (-40 to 105)

ECO Plan:

Green (RoHS & no Sb/Br)

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TPS65218D0RSLT-Integrated Power Management (PMIC) for ARM® Cortex™-A8/A9 SOCs and FPGAs

The TPS65218D0 is a single chip, power-management IC (PMIC) specifically designed to support the AM335x and AM438x line of processors in both portable (Li-Ion battery) and nonportable (5-V adapter) applications. The device provides three step-down converters, three load switches, three general-purpose I/Os, two backup battery supplies, one buck-boost converter, and one LDO. A coin-cell battery can be implemented for backup power to the processor. The device is characterized across a –40°C to +105°C temperature range, making it suitable for various industrial applications.

The TPS65218D0 is specifically designed to provide power management for all the functionalities of the AM438x processor. The DC converters 1 through 4 are intended to power the core, MPU, DDR memory, and 3.3-V analog and I/O, respectively. LDO1 provides the 1.8-V analog and I/O for the processor. GPIO1 and GPO2 allow for memory reset and GPIO3 allows for warm reset (335x only) on the processor. The I2C interface provides comprehensive features for using TPS65218D0. All rails, load switches, and GPIOs can be enabled and disabled. Voltage thresholds for the UVLO and supervisor can be customized. Power-up and power-down sequences can also be programmed through I2C. Interrupts for overtemperature, overcurrent, and undervoltage can be monitored as well. The supervisor monitors DCDC1 through DCDC4 and LDO1. It has two settings, one for typical tolerance for undervoltage (STRICT = 0b), and one for tight tolerances for both undervoltage and overvoltage (STRICT = 1b). A power-good signal follows the rails to determine proper regulation of the five rails.

Three hysteretic step-down converters are targeted at providing power for the core, MPU, and DDRx memory of the processor. The default output voltages for each converter can be adjusted through the I2C interface. DCDC1 and DCDC2 feature dynamic voltage scaling to provide power at all operating points of the processor. DCDC1 and DCDC2 also have programmable slew rates to help protect processor components. DCDC3 remains powered during processor sleep mode to maintain power to DDRx memory. Backup power provides two step-down converters for the tamper, RTC, or both domains of the processor if system power fails or is disabled. If both system power and coin-cell battery are connected to the PMIC, power is not drawn from the coin-cell battery. A separate power good signal monitors the backup converters. A battery backup monitor determines the power level of the coin-cell battery.

The TPS65218D0 device is available in a 48-pin VQFN package (6 mm × 6 mm, 0.4-mm pitch).

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