TSW40RF80EVM 2T2R RF-Sampling Transceiver w/ Dual 14-Bit 3GSPS ADC/9GSPS DAC Clocking Solution Evaluation Module angled board image

TSW40RF80EVM

2T2R RF-Sampling Transceiver w/ Dual 14-Bit 3GSPS ADC/9GSPS DAC Clocking Solution Evaluation Module

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Features for the TSW40RF80EVM

  • RF-sampling transceiver utilizing the JESD204B interface
  • DAC38RF80 dual RF DAC with single-ended output
  • ADC32RF45 dual RF ADC with bypass option
  • LDO-less power-management solution
  • Onboard clocking solution; four different ADC clocking options, including TX PLL clock output
  • Interfaces with TSW14J56 or FPGA development kit with FMC connector

Description for the TSW40RF80EVM

The TSW40RF80 evaluation module (EVM) is a two-transmit two-receive (2T2R) RF-sampling transceiver reference design. The module contains the DAC38RF80 dual-channel RF-sampling digital-to-analog converter (DAC) and the ADC32RF45 dual-channel RF-sampling analog-to-digital converter (ADC).

The DAC38RF80 sampling rate operates up to 9 GSPS and includes an onboard PLL/VCO for high-frequency clock generation. The output is single ended for easy interface to 50-Ω circuitry. The ADC32RF45 sampling rate operates up to 3 GSPS. It has an option to use a dual digital down converter in each channel or to bypass it to access the full Nyquist bandwidth.

The TSW40RF80EVM includes the LMK04828 clock generator for providing a reference signal to the DAC PLL and for generating the required SYSREF signals needed for the JESD204B protocol. Also included is the LMX2582 RF synthesizer for providing an ultra-low-phase noise clock solution for the ADC.

The TSW40RF80EVM implements an efficient LDO-less power-management solution using only DC-DC converters for the required power rails. The design fits within a standard FMC-compliant width and interfaces with the TI pattern/capture card solution (TSW14J56), as well as many FPGA development kits.

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