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Data SheetImagePart # DescriptionPackagePINOperating TemperatureProduct Page
CD4027BE CD4027BE-CMOS Dual J-K Master-Slave Flip-Flop N 16 M (-55 to 125)
CD4027BM CD4027BM-CMOS Dual J-K Master-Slave Flip-Flop D 16 M (-55 to 125)
CD4027BNSR CD4027BNSR-CMOS Dual J-K Master-Slave Flip-Flop NS 16 M (-55 to 125)
CD4027BPWR CD4027BPWR-CMOS Dual J-K Master-Slave Flip-Flop PW 16 M (-55 to 125)
CD74AC109M96 CD74AC109M96-Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset D 16 M (-55 to 125)
CD74AC112E CD74AC112E-Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset N 16 M (-55 to 125)
CD74AC112M CD74AC112M-Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset D 16 M (-55 to 125)
CD74ACT109M CD74ACT109M-Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset D 16 M (-55 to 125)
CD74ACT112M96 CD74ACT112M96-Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset D 16 M (-55 to 125)
CD74HC107M96 CD74HC107M96-High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset D 14 M (-55 to 125)
CD74HC109M96 CD74HC109M96-High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset D 16 M (-55 to 125)
CD74HC112E CD74HC112E-High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset N 16 M (-55 to 125)
CD74HC112M96 CD74HC112M96-High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset D 16 M (-55 to 125)
CD74HC112PWR CD74HC112PWR-High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset PW 16 M (-55 to 125)
CD74HC73E CD74HC73E-High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset N 14 M (-55 to 125)
CD74HC73M96 CD74HC73M96-High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset D 14 M (-55 to 125)
CD74HCT112E CD74HCT112E-High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset N 16 M (-55 to 125)
CD74HCT73E CD74HCT73E-High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset N 14 M (-55 to 125)
CD74HCT73M CD74HCT73M-High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset D 14 M (-55 to 125)
SN74ALS109AN SN74ALS109AN-Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset N 16 C (0 to 70)
SN74ALS112AN SN74ALS112AN-Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset N 16 C (0 to 70)
SN74AS109ANSR SN74AS109ANSR-Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset NS 16 C (0 to 70)
SN74F109DR SN74F109DR-Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset D 16 C (0 to 70)
SN74F112DR SN74F112DR-Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset D 16 C (0 to 70)
SN74F112NSR SN74F112NSR-Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset NS 16 C (0 to 70)

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